Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof

ABSTRACT

A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of Application Ser. No. 10/083,131 filedon Feb. 30, 2004. The submission is in compliance with the provision of37 CFR 1.97. Accordingly, the information disclosure state is beingconsidered by the examiner.

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2001-401999, filed Dec. 28,2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a manufacturing method of a partial SOI wafer,a semiconductor device using the partial SOI wafer and a manufacturingmethod thereof and more particularly to a manufacturing method of apartial SOI wafer having a non-SOI region formed therein by removing aBOX (Buried OXide) layer and silicon layer on a partial region of an SOI(Silicon On Insulator) substrate, a semiconductor device having elementsformed in an SOI region and non-SOI region of the partial SOI wafer anda manufacturing method thereof.

2. Description of the Related Art

A DRAM including memory cells each having one MOSFET and one capacitoris suitable high density integration and is used in various applicationsas an inexpensive large-capacity memory. Particularly, in recent years,it is strongly required to develop a system LSI which is configured byintegrating the DRAM and a logic circuit on a single semiconductor chipto enhance the system performance.

On the other hand, in order to enhance the performance of the logiccircuit configured by mainly using MOSFETs, much attention is given to astructure in which MOSFETs are formed not in a silicon substrate, whichis widely used in the prior art, but in a thin-film SOI substrate, andproducts are already available for some applications as high-performancelogic devices.

Particularly, demand for a system LSI having the high-performance logiccircuit and DRAM mounted thereon is strong and it is desired to developthe technique for forming the DRAM together with the logic circuit whoseperformance is enhanced by use of the SOI structure. In this trend, itis strongly required to develop a system LSI having a DRAM mounted on ahigh-performance logic chip configured by use of the SOI structure.

In order to meet the above requirement, it is considered that the aboveelements are selectively formed on an SOI wafer having an SOI region anda non-SOI region (a region formed by partially removing a BOX layer ofthe SOI substrate).

However, although a MOSFET formed on the SOI substrate has a brightfuture as a high-performance logic device, it is known that a parasiticMOSFET or parasitic bipolar transistor is operated depending on thesource-drain voltage condition due to a so-called substrate-floatingeffect when gate voltage which turns OFF the MOSFET is applied and aleak current flows in the source-drain path. The above characteristiccauses a problem of, for example, deterioration of retention forapplications in which the specification for the leak current is strict,as in a memory cell transistor of a DRAM, for example, and is notpreferable. Further, in the sense amplifier circuit of a DRAM, since thethreshold voltages-of the paired transistors are shifted due to thesubstrate-floating effect, the sense margin is lowered. Due to the aboveproblems, it is difficult to form a DRAM with the same MOSFET structureas the high-performance logic circuit on the SOI substrate.

In order to completely cancel the substrate-floating effect, it isnecessary to form a contact region and a lead-out region from the bodysection of each MOSFET and control the body potential. However, in orderto meet the above requirement, the cell area and the area of the senseamplifier section are made extremely large, thereby losing the highintegration density which is the best feature of a DRAM.

In order to solve the above problem, various methods for using asubstrate (which is hereinafter referred to as a partial non-SOI wafer)obtained by forming a non-SOI region in an SOI substrate, forming ahigh-performance logic circuit on the SOI region and forming a circuitwhich is affected by the substrate-floating effect on the non-SOI regionare proposed. The isolation technique by use of an STI (Shallow TrenchIsolation) region for isolation between the SOI region and the non-SOIregion of the partial SOI wafer is proposed with much attention paid tothe depth of the BOX layer and the depth of the STI region (for example,Jpn. Pat. Appln. KOKAI Publication No. 08-17694), but a connectionstructure between the BOX layer and the STI region is not described.

The volume of an oxide existing on a chip formed by use of a siliconbalk wafer is much smaller than the volume of silicon, since the oxidecontains only a buried oxide in the STI region except the gate oxidefilm. On the other hand, the volume of oxide in the partial SOI waferbecomes equal to the volume thereof in the “BOX layer+STI region” and ismuch larger than the volume of the oxide in the bulk wafer. Therefore,the stress applied to the silicon layer becomes larger accordingly andcrystal defects tend to occur in the non-SOI region. Further, since theSTI region lies in the end portion of the oxide with the large volume,particularly, in a case where the BOX layer and STI region arecontinuously formed, crystal defects tend to occur in the non-SOI regionand it is difficult to obtain a high-quality partial SOI wafer unlessmuch attention is paid to the shape thereof.

As described above, with the conventional partial SOI wafermanufacturing method, crystal defects tend to occur in the non-SOIregion and the quality thereof is lowered by concentration of the stressdue to a difference in the volume of the oxide between the SOI regionand the non-SOI region.

Further, in the conventional semiconductor device using the partial SOIwafer and the manufacturing method thereof, the integration density islowered if an attempt is made to attain high speed operation and highperformance.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided apartial SOI wafer manufacturing method comprising selectively removingpart of a buried oxide layer and a first silicon layer on an SOIsubstrate having the first silicon layer formed on a semiconductorsubstrate with the buried oxide layer disposed therebetween, forming aprotection film to cover a remaining portion of the first silicon layer,forming a second silicon layer by use of an epitaxial growth method onthat part of the semiconductor substrate from which the first siliconlayer and buried oxide layer are removed, forming a trench to reach atleast the buried oxide layer in a boundary portion between the first andsecond silicon layers by anisotropic etching, and burying an isolationinsulating material into the trench, wherein an angle made by the bottomsurface of the trench with the side surface of the second silicon layeris an obtuse angle or a portion near a contact portion of the bottomsurface of the trench with the second silicon layer has a curvedsurface.

According to another aspect of the present invention, there is provideda semiconductor device manufacturing method comprising selectivelyremoving part of a buried oxide layer and a first silicon layer on anSOI substrate having the first silicon layer formed on a semiconductorsubstrate with the buried oxide layer disposed therebetween, forming aprotection film to cover a remaining portion of the first silicon layer,forming a second silicon layer by use of an epitaxial growth method onthat part of the semiconductor substrate from which the first siliconlayer and buried oxide layer are removed, forming a trench to reach atleast the buried oxide layer in a boundary portion between the first andsecond silicon layers, burying an isolation insulating material into thetrench, and respectively forming first and second elements in the firstand second silicon layers, wherein an angle made by the bottom surfaceof the trench with the side surface of the second silicon layer is anobtuse angle or a portion near a contact portion of the bottom surfaceof the trench with the second silicon layer has a curved surface.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating asemiconductor device according to a first embodiment of this invention;

FIG. 1B is an enlarged view showing the lower portion of the STI regionsurrounded by broken lines in FIG. 1A;

FIG. 1C is an enlarged view showing another example of the lower portionof the STI region surrounded by broken lines in FIG. 1A;

FIGS. 2A to 2G are cross sectional views sequentially showingmanufacturing steps in order, for illustrating a partial SOI wafermanufacturing method and a semiconductor device manufacturing methodaccording to the first embodiment of this invention;

FIG. 3A is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating asemiconductor device according to a second embodiment of this invention;

FIG. 3B is an enlarged view showing the lower portion of the STI regionsurrounded by broken lines in FIG. 3A;

FIG. 3C is an enlarged view showing another example of the lower portionof the STI region surrounded by broken lines in FIG. 3A;

FIGS. 4A to 4H are cross sectional views sequentially showingmanufacturing steps in order, for illustrating a partial SOI wafermanufacturing method and a semiconductor device manufacturing methodaccording to the second embodiment of this invention;

FIG. 5A is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating asemiconductor device according to a third embodiment of this invention;

FIG. 5B is an enlarged view showing the lower portion of the STI regionsurrounded by broken lines in FIG. 3A;

FIG. 5C is an enlarged view showing another example of the lower portionof the STI region surrounded by broken lines in FIG. 3A;

FIGS. 6A to 6H are cross sectional views sequentially showingmanufacturing steps in order, for illustrating a partial SOI wafermanufacturing method and a semiconductor device manufacturing methodaccording to the third embodiment of this invention;

FIG. 7 is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating amodification of the semiconductor device according to the secondembodiment of this invention; and

FIG. 8 is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating amodification of the semiconductor device according to the thirdembodiment of this invention.

DETAILED DESCRIPTION OF THE INVENTION

[First Embodiment]

FIG. 1A is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating asemiconductor device according to a first embodiment of this inventionand FIGS. 1B and 1C are enlarged views each showing the lower portion ofthe STI region surrounded by broken lines 20 in FIG. 1A.

On a silicon substrate 1 in the SOI region, a buried oxide layer (BOXlayer) 2 is formed and a silicon layer 3 is formed on the BOX layer 2.Further, on the silicon substrate 1 in the non-SOI region (or bulkregion), an epitaxial silicon layer 5 is formed. An element isolationtrench 12 is formed in a boundary portion between the SOI region and thenon-SOI region to such a depth as to reach the silicon substrate 1 andan insulating layer for isolation (STI element isolation film) 13 isburied in the trench 12. The bottom surface of the isolation insulatinglayer 13 is formed in contact with the silicon substrate 1, and as shownin FIG. 1B, an angle made by the bottom surface of the isolationinsulating layer 13 and the side surface of the epitaxial silicon layer5 is an obtuse angle (19A) by the presence of a facet 19 formed on thatpart of the epitaxial silicon layer 5 which lies near the isolationinsulating layer 13. Alternatively, as shown in FIG. 1C, a portion nearthe contact portion of the bottom surface of the isolation insulatinglayer 13 with the epitaxial silicon layer 5 has a curved surface 19B. Inthis case, a portion of the isolation insulating layer 13 which lies onthe BOX layer 2 side is engaged with the projecting portion of the lowerportion of the BOX layer 2 and formed with an acute angle (19C).

For example, MOSFETs QA-1, QA-2, . . . configuring a logic circuit areformed in the silicon layer 3 and elements such as MOSFETs QB-1, QB-2, .. . configuring memory cells and sense amplifier circuit of a DRAM areformed in the epitaxial silicon layer 5. An inter-level insulating film14 is formed on the silicon layer 3, epitaxial silicon layer 5 andisolation insulating layer 13. Contact holes 15A-1, 15A-2, . . . ,15B-1, 15B-2, . . . are formed in corresponding positions of theinter-level insulating film 14 which lie on the source and drain regionsof the MOSFETs QA-1, QA-2, . . . , QB-1, QB-2, . . . Further,interconnection layers 16A-1, 16A-2, . . . , 16B-1, 16B-2, . . . areformed on the inter-level insulating film 14 and connected to therespective source and drain regions of the MOSFETs QA-1, QA-2, . . . ,QB-1, QB-2, . . . via the contact holes 15A-1, 15A-2, . . . , 15B-1,15B-2, . . . A surface protection film 17 is formed on theinterconnection layers 16A-1, 16A-2, . . . , 16B-1, 16B-2, . . . andinter-level insulating film 14.

With the above structure, occurrence of crystal defects in the epitaxialsilicon layer 5 due to concentration of the stress on the boundaryportion between the oxide film and silicon can be suppressed. The reasonfor this is that an obtuse angle is made by the bottom surface of theisolation insulating layer 13 with the side surface of the non-SOIregion as shown in FIG. 1B or the bottom surface of the isolationinsulating layer 13 is formed in smooth contact with the epitaxialsilicon layer 5 to provide a curved surface as shown in FIG. 1C. Thatis, there occurs no problem in an element isolation region formed in thewafer having only the SOI region or non-SOI region, but even if a waferhaving a boundary between the SOI region and the non-SOI region is used,occurrence of a problem that crystal defects will occur in the wafer canbe suppressed. This is because the volume of the oxide in the SOI regionis larger than that in the non-SOI region and concentration of thestress can be suppressed by the smooth contact portion (19A or 19B) evenif the stress applied to the epitaxial silicon layer 5 is large. Theright-angled portion (acute angle portion) 19C is formed in the SOIregion, but even if crystal defects occur from the right-angled portion19C as an origin, no influence is given to the elements on the SOIregion or non-SOI region as far as the defects extend into the siliconsubstrate 1 of the SOI region and, therefore, there occurs no problem.

Further, since it is not necessary to form a contact region and alead-out region from the body section of each MOSFET for controlling thebody potential, the cell area and the area of the sense amplifiersection will not increase. Therefore, a high speed and high performancesemiconductor device can be formed without losing the feature of highintegration density when the partial SOI wafer is used.

Next, a manufacturing method of the partial SOI wafer and semiconductordevice shown in FIG. 1A is explained with reference to FIGS. 2A to 2G.

First, an oxide layer 2 which will be used as a BOX layer is formed on asilicon substrate 1 and a silicon layer 3 is formed on the oxide layer 2to form an SOI wafer. Alternatively, the silicon layer 1, BOX layer 2and silicon layer 3 are stacked by use of a lamination method to form anSOI wafer.

Then, as shown in FIG. 2A, after part of the silicon layer 3 on the SOIwafer which is formed in the non-SOI region is removed by anisotropicetching such as RIE, part of the BOX layer 2 is removed by isotropicetching by use of a solution. In this case, anisotropic etching such asRIE can be used instead of isotropic etching to remove part of the BOXlayer 2.

After this, a silicon nitride layer used as a protection film 4 isformed to cover the silicon layer 3. In this example, the siliconnitride layer is used as the protection film 4, but a silicon oxidelayer can be used in the same manner.

Next, part of the BOX layer 2 which remains on the non-SOI region isetched and removed (refer to FIG. 2B). As the etching process, wetetching using a solution is used instead of etching using ions. By useof the wet etching, occurrence of damage on the surface of the siliconsubstrate 1 in the non-SOI region caused by application of ions can beprevented.

Then, as shown in FIG. 2C, an epitaxial silicon layer 5 is formed on thesilicon substrate 1 in the non-SOI region. Since the protection film 4is formed on the SOI region, the epitaxial silicon layer 5 is not formedthereon. At this time, the epitaxial growth is performed in a conditionthat a facet 10 is formed on a portion near the boundary of the surfaceregion of the epitaxial silicon layer 5 with the SOI region. Forexample, the facet 10 can be formed by growing the epitaxial siliconlayer 5 at 10 Torr. Further, the height of the surface of the epitaxialsilicon layer 5 can be set to the same height as or a different heightfrom the surface of the SOI region and freely adjusted by adjusting thetime of the epitaxial growth. The height of the epitaxial silicon layer5 can be freely set as required.

After this, as shown in FIG. 2D, a mask member 6 is deposited and formedon the protection film 4 and epitaxial silicon layer 5. In the presentembodiment, a silicon nitride layer is used as the mask member 6 andrepresented integrally with the protection film 4.

Next, a region other than a region which configures the STI region iscovered with a photomask 18 and part of the silicon nitride layer 6 usedas the mask member 6 is removed. At this time, the silicon nitride layer6 is over-etched to expose the facet 10 of the epitaxial silicon layer 5(refer to FIG. 2E).

Then, as shown in FIG. 2F, portions of the protection film 4 (SiN),silicon layer 3, epitaxial silicon layer 5 (Si) and BOX layer 2 (SiO₂)which lie near the boundary portion between the SOI region and thenon-SOI region are dry-etched by a method such as RIE in order to forman element isolation trench 12. In the above etching process, thecondition in which SiN, SiO₂ and Si can be etched at substantially thesame etching rate is used. The depth of the trench 12 will vary with theetching time, but in any depth, it is possible to form the trench 12 inwhich the bottom surface thereof is coupled with the side surfacethereof at an angle of 90° or more (obtuse angle) at least on thenon-SOI region side of the trench 12 by the presence of the facet 10.Depending on the etching condition, a portion near the contact portionof the bottom surface of the trench 12 with the non-SOI region may beformed to have a curved surface. It is sufficient if the trench 12 isformed to such a depth as to reach at least the BOX layer 2 and thetrench can be formed to extend into the silicon substrate 1.

Next, as shown in FIG. 2G, an isolation insulating layer 13 is filled orburied in the trench 12 to form an element isolation region of STIstructure.

After this, the mask member (silicon nitride layer) 6 on the siliconlayer 3 and epitaxial silicon layer 5 is removed, and MOSFETs QA-1,QA-2, . . . configuring a logic circuit are formed in the silicon layer3 and elements such as MOSFETs QB-1, QB-2, . . . configuring memorycells and sense amplifier circuit of a DRAM are formed in the epitaxialsilicon layer 5 by use of a known process so as to form a semiconductordevice as shown in FIG. 1A.

In this case, the MOSFETs QA-1, QA-2, . . . and MOSFETs QB-1, QB-2, . .. can be formed in different steps or can be formed by commonly usingpart or all of the steps.

According to the above manufacturing method, since the lower end portionof the STI element isolation film 13 can be formed in smooth contactwith the epitaxial silicon layer 5 by use of the facet 10, entrance ofcrystal defects into the epitaxial silicon layer 5 by concentration ofthe stress on the boundary portion between the oxide film and siliconcan be suppressed. As a result, since crystal defects are difficult toenter the non-SOI region, a partial SOI wafer of high quality can beprovided. Further, since it is not necessary to form a contact regionand a lead-out region from the body section of each MOSFET forcontrolling the body potential, the cell area and the area of the senseamplifier section will not increase. Therefore, a high speed and highperformance semiconductor device and a manufacturing method thereof canbe attained without losing the feature of high integration density whenthe partial SOI wafer is used.

[Second Embodiment]

FIG. 3A is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating asemiconductor device according to a second embodiment of this inventionand FIGS. 3B and 3C are enlarged views showing the lower portion of theSTI region surrounded by broken lines 21 in FIG. 3A.

The semiconductor device according to the second embodiment hasbasically the same configuration as the first embodiment, the samereference numerals are attached to portions similar to those of FIG. 1Aand the detail explanation thereof is omitted.

In the semiconductor device according to the second embodiment, like thefirst embodiment, a silicon layer and BOX layer are partly removed whena non-SOI region is formed and silicon is epitaxially grown on thenon-SOI region of the silicon substrate. At this time, a cavity isformed in a boundary portion between the epitaxial silicon layer and theSOI region. Then, as shown in FIG. 3B, an obtuse angle 19A is made bythe bottom surface of the isolation insulating layer 13 with the sidesurface of the epitaxial silicon layer 5 by use of the cavity, or asshown in FIG. 3C, a portion near the contact portion of the bottomsurface of the isolation insulating layer 13 with the epitaxial siliconlayer 5 is smoothly formed to have a curved surface 19B.

That is, an oxide layer 2 used as the BOX layer is formed on the siliconsubstrate 1 and a silicon layer 3 is formed on the oxide layer 2 to forman SOI wafer. Alternatively, the silicon layer 1, BOX layer 2 andsilicon layer 3 are stacked by use of a lamination method to form an SOIwafer.

Then, as shown in FIG. 4A, after part of the silicon layer 3 on the SOIwafer which is formed in the non-SOI region is removed by anisotropicetching such as RIE, part of the BOX layer 2 is removed by isotropicetching by use of a solution. Of course, in this case, anisotropicetching such as RIE can be used instead of isotropic etching to removepart of the BOX layer 2.

After this, a protection film 4 formed of silicon nitride or the like isformed to cover the silicon layer 3. In this example, silicon nitride isused to form the protection film 4, but silicon oxide can be used in thesame manner.

Next, part of the BOX layer 2 which remains on the non-SOI region isetched and removed (refer to FIG. 4B). As the etching process, wetetching using a solution is used instead of etching using ions. By useof the wet etching, occurrence of damage on the surface of the siliconsubstrate 1 in the non-SOI region caused by application of ions can beprevented. Further, the etching time is made longer than in the firstembodiment so that the etching process may proceed in the lateraldirection.

Then, as shown in FIG. 4C, an epitaxial silicon layer 5 is formed on thesilicon substrate 1 in the non-SOI region. Since the protection film 4is formed on the SOI region, the epitaxial silicon layer 5 is not formedthereon. At this time, a facet is formed on a portion near the boundaryof the surface region of the epitaxial silicon layer 5 with the SOIregion, and a facet portion which is formed on the inner side of theside wall of the protection film 4 remains as a cavity 11. Of course,like the first embodiment, the height of the surface of the epitaxialsilicon layer 5 can be set to the same height as or a different heightfrom the surface of the SOI region and freely adjusted by adjusting thetime of the epitaxial growth. Therefore, the height of the epitaxialsilicon layer 5 can be freely set as required.

After this, as shown in FIG. 4D, a mask member 6 is deposited and formedon the protection film 4 and epitaxial silicon layer 5. In the presentembodiment, a silicon nitride layer is used as the mask member 6 andrepresented integrally with the protection film 4.

Next, a region other than a region which configures the STI region iscovered with a photomask 18 (refer to FIG. 4E) and part of the siliconnitride layer used as the mask member 6 is removed (refer to FIG. 4F).

Then, as shown in FIG. 4G, portions of the protection film 4 (SiN),silicon layer 3, epitaxial silicon layer 5 (Si) and BOX layer 2 (SiO₂)which lie near the boundary portion between the SOI region and thenon-SOI region are dry-etched by a method such as RIE in order to forman element isolation trench 12. In the above etching process, thecondition in which SiN, SiO₂ and Si can be etched at substantially thesame etching rate is used. The depth of the trench 12 will vary with theetching time, but in any depth, it is possible to form the trench 12 inwhich the bottom surface thereof is coupled with the side surfacethereof at an angle of 90° or more (obtuse angle 19A) at least on thenon-SOI region side of the trench 12 by the presence of the cavity 11.Depending on the etching condition, a portion near the coupling portionof the bottom surface of the trench 12 on the non-SOI region side isformed to have a curved surface 19B. It is sufficient if the trench 12is formed to such a depth as to reach at least the BOX layer 2 and thetrench can be formed to extend into the silicon substrate 1.

Next, as shown in FIG. 4H, an insulating layer for isolation 13 isfilled or buried in the trench 12 to form an element isolation region ofSTI structure.

After this, the mask member 6 on the silicon layer 3 and epitaxialsilicon layer 5 is removed, and MOSFETs QA-1, QA-2, . . . configuring alogic circuit are formed in the silicon layer 3 and elements such asMOSFETs QB-1, QB-2, . . . configuring memory cells and sense amplifiercircuit of a DRAM are formed in the epitaxial silicon layer 5 by use ofa known process so as to form a semiconductor device as shown in FIG.3A.

In this case, the MOSFETs QA-1, QA-2, . . . and MOSFETs QB-1, QB-2, . .. can be formed in different steps or can be formed by commonly usingpart or all of the steps.

According to the above manufacturing method, since the lower end portionof the STI element isolation film 13 can be formed in smooth contactwith the epitaxial silicon layer 5 by use of the cavity 11, entrance ofcrystal defects into the epitaxial silicon layer 5 by concentration ofthe stress in the boundary portion between the oxide film and siliconcan be suppressed. As a result, since crystal defects are difficult toenter the non-SOI region, a partial SOI wafer of high quality can beprovided. Further, since it is not necessary to form a contact regionand a lead-out region from the body section of each MOSFET forcontrolling the body potential, the cell area and the area of the senseamplifier section will not increase. Therefore, a high speed and highperformance semiconductor device and a manufacturing method thereof canbe attained without losing the feature of high integration density whenthe partial SOI wafer is used.

[Third Embodiment]

FIG. 5A is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating asemiconductor device according to a third embodiment of this inventionand FIGS. 5B and 5C are enlarged views showing the lower portion of theSTI region surrounded by broken lines 22 in FIG. 5A.

The semiconductor device according to the third embodiment has basicallythe same configuration as the first and second embodiments, the samereference numerals are attached to portions similar to those of FIG. 1Aor FIG. 3A and the detail explanation thereof is omitted.

The semiconductor device according to the third embodiment is configuredby combining the first and second embodiments, and in the semiconductordevice, a silicon layer and BOX layer are partially removed when anon-SOI region is formed and then silicon is epitaxially grown on thenon-SOI region of the silicon substrate. At this time, a facet andcavity are formed in a boundary portion between the epitaxial siliconlayer and an SOI region. Then, as shown in FIG. 5B, an obtuse angle 19Ais made by the bottom surface of an isolation insulating layer 13 andthe side surface of the epitaxial silicon layer 5, or as shown in FIG.5C, a portion near the contact portion of the bottom surface of theisolation insulating layer 13 with the epitaxial silicon layer 5 issmoothly formed to have a curved surface 19B by use of the facet andcavity.

That is, an oxide layer 2 used as the BOX layer is formed on the siliconsubstrate 1 and a silicon layer 3 is formed on the oxide layer 2 to forman SOI wafer. Alternatively, the silicon layer 1, BOX layer 2 andsilicon layer 3 are stacked by use of a lamination method to form an SOIwafer.

Then, as shown in FIG. 6A, after part of the silicon layer 3 on the SOIwafer which is formed in the non-SOI region is removed by anisotropicetching such as RIE, part of the BOX layer 2 is removed by isotropicetching by use of a solution. In this case, anisotropic etching such asRIE can be used instead of isotropic etching to remove part of the BOXlayer 2.

After this, a protection film 4 formed of silicon nitride or the like isformed to cover the silicon layer 3. In this example, silicon nitride isused to form the protection film 4, but silicon oxide can be used in thesame manner.

Next, part of the BOX layer 2 which remains on the non-SOI region isremoved by etching (refer to FIG. 6B). As the etching process, wetetching using a solution is used instead of etching using ions. By useof the wet etching, occurrence of damage on the surface of the siliconsubstrate 1 in the non-SOI region caused by application of ions can beprevented. Further, like the second embodiment, the etching time is madelonger than in the first embodiment so that the etching process mayproceed in the lateral direction.

Then, as shown in FIG. 6C, an epitaxial silicon layer 5 is formed on thesilicon substrate 1 in the non-SOI region. Since the protection film 4is formed on the SOI region, the epitaxial silicon layer 5 is not formedthereon. At this time, a facet 10 is formed on a portion near theboundary of the surface region of the epitaxial silicon layer 5 with theSOI region. Further, a facet portion which is formed on the inner sideof the side wall of the protection film 4 remains as a cavity 11. Ofcourse, like the first and second embodiments, the height of the surfaceof the epitaxial silicon layer 5 can be set to the same height as or adifferent height from the surface of the SOI region and freely adjustedby adjusting the time of the epitaxial growth. Therefore, the height ofthe epitaxial silicon layer 5 can be freely set as required.

After this, as shown in FIG. 6D, a mask member 6 is deposited and formedon the protection film 4 and epitaxial silicon layer 5. In the presentembodiment, a silicon nitride layer is used as the mask member 6 andrepresented integrally with the protection film 4.

Next, a region other than a region which configures the STI region iscovered with a photomask 18 (refer to FIG. 6E) and part of the siliconnitride layer 6 is removed (refer to FIG. 6F).

Then, as shown in FIG. 6G, portions of the protection film 4 (SiN),silicon layer 3, epitaxial silicon layer 5 (Si) and BOX layer 2 (SiO₂)which lie near the boundary portion between the SOI region and thenon-SOI region are dry-etched by a method such as RIE in order to forman element isolation trench 12. In the above etching process, thecondition in which SiN, SiO₂ and Si can be etched at substantially thesame etching rate is used. The depth of the trench 12 will vary with theetching time, but in any depth, it is possible to form the trench 12 inwhich the bottom surface thereof is coupled with the side surfacethereof at an angle of 90° or more (obtuse angle 19A) at least on thenon-SOI region side of the trench 12 by the presence of the facet 10 andcavity 11. Depending on the etching condition, a portion near thecontact portion of the bottom surface of the trench 12 with the non-SOIregion is formed to have a curved surface 19B. It is sufficient if thetrench 12 is formed to such a depth as to reach at least the BOX layer 2and the trench can be formed to extend into the silicon substrate 1.

Next, as shown in FIG. 6H, an insulating layer for isolation 13 isfilled or buried in the trench 12 to form an element isolation region ofSTI structure.

After this, the mask member 6 on the silicon layer 3 and epitaxialsilicon layer 5 is removed, and MOSFETs QA-1, QA-2, . . . configuring alogic circuit are formed in the silicon layer 3 and elements such asMOSFETs QB-1, QB-2, . . . configuring memory cells and sense amplifiercircuit of a DRAM are formed in the epitaxial silicon layer 5 by use ofa known process so as to form a semiconductor device as shown in FIG.5A.

As explained in the first and second embodiments, the MOSFETs QA-1,QA-2, . . . and MOSFETs QB-1, QB-2, . . . can be formed in differentsteps or can be formed by commonly using part or all of the steps.

According to the above manufacturing method, since the lower end portionof the STI element isolation film 13 can be formed in smooth contactwith the epitaxial silicon layer 5 by use of the facet 10 and cavity 11,entrance of crystal defects into the epitaxial silicon layer 5 byconcentration of the stress in the boundary portion between the oxidefilm and silicon can be suppressed. As a result, since crystal defectsare difficult to enter the non-SOI region, a partial SOI wafer of highquality can be provided. Further, since it is not necessary to form acontact region and a lead-out region from the body section of eachMOSFET for controlling the body potential, the cell area and the area ofthe sense amplifier section will not increase. Therefore, a high speedand high performance semiconductor device and a manufacturing methodthereof can be attained without losing the feature of high integrationdensity when the partial SOI wafer is used.

In the second and third embodiments, the element isolation region isformed so as not to leave behind the cavity 11 when the elementisolation region of STI structure is formed by burying or filling theisolation insulating layer 13 in the trench 12. However, as shown inFIGS. 7 and 8, even if the cavity 11 is left behind under the isolationinsulating layer 13, the stress between the oxide film and silicon canbe alleviated and the same effect and function can be attained.

FIG. 7 is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating amodification of the semiconductor device according to the secondembodiment of this invention. As shown in FIG. 7, a cavity 11 is leftbehind under the isolation insulating layer 13.

FIG. 8 is a cross sectional view showing an STI region in a boundaryportion between an SOI region and a non-SOI region, for illustrating amodification of the semiconductor device according to the thirdembodiment of this invention. As shown in FIG. 8, a cavity 11 is leftbehind under the isolation insulating layer 13.

Further, in the above embodiments, the epitaxial silicon layer 5 isformed on the silicon substrate 1 in the non-SOI region and elementssuch as MOSFETs are formed in the epitaxial silicon layer 5, but it isalso possible to form the elements in a bulk, that is, in the siliconsubstrate 1.

As described above, according to one aspect of this invention, amanufacturing method of a partial SOI wafer of high quality in whichcrystal defects are difficult to enter the non-SOI region can beattained.

Further, a high speed and high performance semiconductor device and amanufacturing method thereof can be attained without losing the featureof high integration density when the partial SOI wafer is used.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A partial SOI wafer manufacturing method comprising: selectivelyremoving part of a buried oxide layer and first silicon layer on an SOIsubstrate having the first silicon layer formed on a semiconductorsubstrate with the buried oxide layer disposed therebetween, forming aprotection film to cover a remaining portion of the first silicon layer,forming a second silicon layer by use of an epitaxial growth method onthat part of the semiconductor substrate from which the first siliconlayer and buried oxide layer are removed, forming a trench to reach atleast the buried oxide layer in a boundary portion between the first andsecond silicon layers by anisotropic etching, and burying an isolationinsulating material into the trench, wherein an angle made by the bottomsurface of the trench with the side surface of the second silicon layeris an obtuse angle or a portion near a contact portion of the bottomsurface of the trench with the second silicon layer has a curvedsurface.
 2. The partial SOI wafer manufacturing method according toclaim 1, wherein a condition for epitaxial growth in forming the secondsilicon layer is a condition for forming a facet on a portion near acontact portion of the surface region of the second silicon layer withthe buried oxide layer.
 3. The partial SOI wafer manufacturing methodaccording to claim 1, wherein a condition for epitaxial growth informing the second silicon layer is a condition for forming a cavity ina portion near a contact portion between the protection film and theburied oxide layer.
 4. The partial SOI wafer manufacturing methodaccording to claim 1, wherein a condition for epitaxial growth informing the second silicon layer is a condition for forming a facet on aportion near a contact portion of the surface region of the secondsilicon layer with the buried oxide layer and forming a cavity in aportion near a contact portion between the protection film and theburied oxide layer.
 5. The partial SOI wafer manufacturing methodaccording to claim 1, wherein said anisotropic etching for forming thetrench is performed under a condition that the first silicon layer,protection film, buried oxide layer and second silicon layer are etchedat substantially the same rate.
 6. A semiconductor device manufacturingmethod comprising: selectively removing part of a buried oxide layer andfirst silicon layer on an SOI substrate having the first silicon layerformed on a semiconductor substrate with the buried oxide layer disposedtherebetween, forming a protection film to cover a remaining portion ofthe first silicon layer, forming a second silicon layer by use of anepitaxial growth method on that part of the semiconductor substrate fromwhich the first silicon layer and buried oxide layer are removed,forming a trench to reach at least the buried oxide layer in a boundaryportion between the first and second silicon layers, burying anisolation insulating material into the trench, and respectively formingfirst and second elements in the first and second silicon layers,wherein an angle made by the bottom surface of the trench with the sidesurface of the second silicon layer is an obtuse angle of a portion neara contact portion of the bottom surface of the trench with the secondsilicon layer has a curved surface.
 7. The semiconductor devicemanufacturing method according to claim 6, wherein a condition forepitaxial growth in forming the second silicon layer is a condition forforming a facet on a portion near a contact portion of the surfaceregion of the second silicon layer with the buried oxide layer.
 8. Thesemiconductor device manufacturing method according to claim 6, whereina condition for epitaxial growth in forming the second silicon layer isa condition for forming a cavity in a portion near a contact portionbetween the protection film and the buried oxide layer.
 9. Thesemiconductor device manufacturing method according to claim 6, whereina condition for epitaxial growth in forming the second silicon layer isa condition for forming a facet on a portion near a contact portion ofthe surface region of the second silicon layer with the buried oxidelayer and forming a cavity in a portion near a contact portion betweenthe protection film and the buried oxide layer.
 10. The semiconductordevice manufacturing method according to claim 6, wherein said formingthe trench is performed under a condition that the first silicon layer,protection film, buried oxide layer and second silicon layer are etchedat substantially the same rate.